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| ds07-13714-1e fujitsu semiconductor data sheet 16-bit proprietary microcontroller cmos f 2 mc-16lx mb90460 series mb90462/467/f462/v460 n n n n description the mb90460 series is a line of general-purpose, fujitsu 16-bit microcontrollers designed for process control applications which require high-speed real-time processing, such as consumer products. while inheriting the at architecture of the f 2 mc * family, the instruction set for the f 2 mc-16lx cpu core of the mb90460 series incorporates additional instructions for high-level languages, supports extended addressing modes, and contains enhanced multiplication and division instructions as well as a substantial collection of improved bit manipulation instructions. in addition, the mb90460 has an on-chip 32-bit accumulator which enables processing of long-word data. the peripheral resources integrated in the mb90460 series include : an 8/10-bit a/d converter, uarts (sci) 0 to 1, 16-bit ppg timer, a multi-functional timer (16-bit free-run timer, input capture units (icus) 0 to 3, output compare units (ocus) 0 and 5, 16-bit ppg timer, a waveform generator) , a multi-pulse generator (16-bit ppg timer, 16-bit reload timer, waveform sequencer) , pwc 0 to 1, 16-bit reload timer and dtp/external interrupt. * : f 2 mc stands for fujitsu flexible microcontroller, a registered trademark of fujitsu limited. n n n n features ? minimum execution time : 62.5 ns/4 mhz oscillation (uses pll clock multiplication) maximum multiplier = 4 ? maximum memory space 16 mbyte linear/bank access (continued) n n n n packages 64-pin plastic qfp 64-pin plastic lqfp 64-pin plastic sh-dip (fpt-64p-m06) (fpt-64p-m09) (dip-64p-m01)
mb90460 series 2 (continued) ? instruction set optimized for controller applications supported data types : bit, byte, word, and long-word types standard addressing modes : 23 types 32-bit accumulator enhancing high-precision operations signed multiplication/division and extended reti instructions ? enhanced high level language (c) and multi-tasking support instructions use of a system stack pointer symmetrical instruction set and barrel shift instructions ? program patch function (for two address pointers) ? enhanced execution speed : 4 byte instruction queue ? enhanced interrupt function up to eight programmable priority levels external interrupt inputs : 8 lines ? automatic data transmission function independent of cpu operation up to 16 channels for the extended intelligent i/o service dtp request inputs : 8 lines ? internal rom flash : 64 kbyte (with flash security) maskrom : 64 kbyte ? internal ram eva : 8 kbyte flash : 2 kbyte maskrom : 2 kbyte ? general-purpose ports up to 51 channels (input pull-up resistor settable for : 16 channels) ? a/d converter (rc) : 8 ch 8/10-bit resolution selectable conversion time : 6.13 m s (min) , 16 mhz operation ? uart : 2 channels ? 16 bit ppg : 3 channels mode switching function provided (pwm mode or one-shot mode) can be worked with a multi-functional timer, a multi-pulse generator or individually ? 16 bit reload timer : 2 channels can be worked with multi-pulse generator or individually ? 16-bit pwc timer : 2 channels ? a multi-functional timer input capture : 4 channels output compare with selectable buffer : 6 channels free-run timer with up or up/down mode selection and selectable buffer : 1 channel 16-bit ppg : 1 channel a waveform generator : (16-bit timer : 3 channels, 3-phase waveform or dead time) ? a multi-pulse generator 16-bit ppg : 1 channel 16-bit reload timer : 1 channel waveform sequencer : (16-bit timer with buffer and compare clear function) ? time-base counter/watchdog timer : 18-bit mb90460 series 3 ? low-power consumption mode : sleep mode stop mode cpu intermittent operation mode ? package : qfp-64 (fpt-64p-m09 : 0.65 mm pitch) qfp-64 (fpt-64p-m06 : 1.00 mm pitch) sdip-64 (dip-64p-m01 : 1.78 mm pitch) ?cmos technology mb90460 series 4 n n n n product lineup (continued) item part number mb90v460 mb90f462 mb90462 mb90467 classification development/evaluation product mass-produced products (flash rom) mass-produced products (mask rom) rom size ? 64 kbytes ram size 8 kbytes 2 kbytes cpu function number of instruction : 351 minimum execution time : 62.5 ns / 4 mhz (pll 4) addressing mode : 23 data bit length : 1, 8, 16 bits maximum memory space : 16 mbytes i/o port i/o port (cmos) : 51 pwc pulse width counter timer : 2 channels pulse width counter timer : 1ch timer function (select the counter timer from three internal clocks) various pulse width measuring function (h pulse width, l pulse width, rising edge to fall- ing edge period, falling edge to rising edge period, rising edge to rising edge period and falling edge to falling edge period) uart uart : 2 channels with full-duplex double buffer (8-bit length) clock asynchronized or clock synchronized transmission (with start and stop bits) can be selectively used transmission can be one-to-one (bi-directional commuication) or one-to-n (master- slave communication) 16-bit reload timer reload timer : 2 channels reload mode, single-shot mode or event count mode selectable can be worked with a multi-pulse generator or individually 16-bit ppg timer ppg timer : 3 channels ppg timer : 2ch pwm mode or single-shot mode selectable can be worked with multi-functional timer / multi-pulse generator or individually multi-functional timer (for ac/dc motor control) 16-bit free-running timer with up or up/down mode selection and buffer : 1 channel 16-bit output compare : 6 channels 16-bit input capture : 4 channels 16-bit ppg timer : 1 channel waveform generator (16-bit timer : 3 channels, 3-phase waveform or dead time) multi-pulse generator (for dc motor control) 16-bit ppg timer : 1 channel 16-bit reload timer operation (toggle output, one shot output select- able) event counter function : 1 channel built-in a waveform sequencer (includes 16-bit timer with buffer and com- pare clear function) ? 8/10-bit a/d converter 8/10-bit resolution (8 channels) conversion time : less than 6.13 m s (16 mhz internal clock) dtp/external interrupt 8 independent channels selectable causes : rising edge, falling edge, l level or h level lower power consumption stop mode / sleep mode / cpu intermittent operation mode mb90460 series 5 (continued) * : varies with conditions such as the operating frequency (see section n electrical characteristics) . assurance for the mb90v460 is given only for operation with a tool at a power supply voltage of 4.5 v to 5.5 v, an operating temperature of 0 to + 25 c, and an operating frequency of 1 mhz to 16 mhz. n n n n package and corresponding products : available, : not available note : for more information about each package, see section n package dimensions. n n n n differences among products memory size in evaluation with an evaluation product, note the difference between the evaluation product and the product actually used. the following items must be taken into consideration. ? the mb90v460 does not have an internal rom, however, operations equivalent to chips with an internal rom can be evaluated by using a dedicated development tool, enabling selection of rom size by settings of the development tool. ? in the mb90v460, images from ff4000 h to ffffff h are mapped to bank 00, and fe0000 h to ff3fff h are mapped to bank ff only. (this setting can be changed by configuring the development tool.) ? in the mb90462/f462/467, images from ff4000 h to ffffff h are mapped to bank 00, and ff0000 h to ff3fff h are mapped to bank ff only. item part number mb90v460 mb90f462 mb90462 mb90467 package pga256 lqfp-64 (fpt-64p-m09 : 0.65 mm pitch) qfp-64 (fpt-64p-m06 : 1.00 mm pitch) sdip-64 (dip-64p-m01 : 1.78 mm pitch) power supply voltage for operation* 4.5 v to 5.5 v * process cmos package mb90v460 mb90f462 mb90462 mb90467 pga256 fpt-64p-m09 ftp-64p-m06 dip-64p-m01 mb90460 series 6 n n n n pin assignment (continued) (top view) (fpt-64p-m06) *1 : heavy current pins *2 : mb90v460, mb90f462, mb90462 only. they do not exist on mb90467, because there are not pwc (ch 0) , 16-bit ppg (ch 1) and waveform sequencer. p44/sni1* 2 p45/sni2* 2 p46/ppg2 p50/an0 p51/an1 p52/an2 p53/an3 p54/an4 p55/an5 p56/an6 p57/an7 av cc avr av ss p60/sin1 p61/sot1 p62/sck1 p63/int7 md0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 p30* 1 /rto0 (u) v ss p27/in3 p26/in2 p25/in1 p24/in0 p23/pwo1 p22/pwi1 p21/to1 p20/tin1 p17/frck p16/int6/to0 p15/int5/tin0 p14/int4 p13/int3 p12/int2/dtti1* 2 p11/int1 p10/int0/dtti0 p07/pwo0* 2 64 63 62 61 60 59 58 57 56 55 54 53 52 p43/sni0* 2 p42/sck0 p41/sot0 p40/sin0 p37/ppg0 p36/ppg1* 2 c v cc p35* 1 /rto5 (z) p34* 1 /rto4 (w) p33* 1 /rto3 (y) p32* 1 /rto2 (v) p31* 1 /rto1 (x) 20 21 22 23 24 25 26 27 28 29 30 31 32 rst md1 md2 x0 x1 v ss p00* 1 /opt0* 2 p01* 1 /opt1* 2 p02* 1 /opt2* 2 p03* 1 /opt3* 2 p04* 1 /opt4* 2 p05* 1 /opt5* 2 p06/pwi0* 2 mb90460 series 7 (continued) (top view) (fpt-64p-m09) *1 : heavy current pins *2 : mb90v460, mb90f462, mb90462 only. they do not exist on mb90467, because there are not pwc (ch 0) , 16-bit ppg (ch 1) and waveform sequencer. p45/sni2* 2 p46/ppg2 p50/an0 p51/an1 p52/an2 p53/an3 p54/an4 p55/an5 p56/an6 p57/an7 av cc avr av ss p60/sin1 p61/sot1 p62/sck1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 p27/in3 p26/in2 p25/in1 p24/in0 p23/pwo1 p22/pwi1 p21/to1 p20/tin1 p17/frck p16/int6/to0 p15/int5/tin0 p14/int4 p13/int3 p12/int2/dtti1* 2 p11/int1 p10/int0/dtti0 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 p44/sni1* 2 p43/sni0* 2 p42/sck0 p41/sot0 p40/sin0 p37/ppg0 p36/ppg1* 2 c v cc p35* 1 /rto5 (z) p34* 1 /rto4 (w) p33* 1 /rto3 (y) p32* 1 /rto2 (v) p31* 1 /rto1 (x) p30* 1 /rto0 (u) v ss 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 p63/int7 md0 rst md1 md2 x0 x1 v ss p00* 1 /opt0* 2 p01* 1 /opt1* 2 p02* 1 /opt2* 2 p03* 1 /opt3* 2 p04* 1 /opt4* 2 p05* 1 /opt5* 2 p06/pwi0 p07/pwo0 mb90460 series 8 (continued) (top view) (dip-64p-m01) *1 : heavy current pins *2 : mb90v460, mb90f462, mb90462 only. they do not exist on mb90467, because there are not pwc (ch 0) , 16-bit ppg (ch 1) and waveform sequencer. c p36/ppg1* 2 p37/ppg0 p40/sin0 p41/sot0 p42/sck0 p43/sni0* 2 p44/sni1* 2 p45/sni2* 2 p46/ppg2 p50/an0 p51/an1 p52/an2 p53/an3 p54/an4 p55/an5 p56/an6 p57/an7 av cc avr av ss p60/sin1 p61/sot1 p62/sck1 p63/int7 md0 rst md1 md2 x0 x1 v ss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 v cc p35* 1 /rto5 (z) p34* 1 /rto4 (w) p33* 1 /rto3 (y) p32* 1 /rto2 (v) p31* 1 /rto1 (x) p30* 1 /rto0 (u) v ss p27/in3 p26/in2 p25/in1 p24/in0 p23/pwo1 p22/pwi1 p21/to1 p20/tin1 p17/frck p16/int6/to0 p15/int5/tin0 p14/int4 p13/int3 p12/int2/dtti1* 2 p11/int1 p10/int0/dtti0 p07/pwo0* 2 p06/pwi0* 2 p05* 1 /opt5* 2 p04* 1 /opt4* 2 p03* 1 /opt3* 2 p02* 1 /opt2* 2 p01* 1 /opt1* 2 p00* 1 /opt0* 2 mb90460 series 9 n n n n pin description (continued) pin no. pin name i/o circuit function qfp- m06* 2 lqfp- m09* 1 sdip* 3 23, 24 22, 23 30, 31 x0, x1 a oscillation input pins. 20 19 27 rst b external reset input pin. 26 to 31 25 to 30 33 to 38 p00 to p05 d general-purpose i/o ports. opt0 to opt5 * 4 output terminals opt0 to 5 of the waveform sequencer. these pins output the waveforms specified at the output data registers of the waveform sequencer circuit. output is generated when ope0 to 5 of opcr is enabled. * 4 32 31 39 p06 e general-purpose i/o ports. pwi0 * 4 pwc 0 signal input pin. * 4 33 32 40 p07 e general-purpose i/o ports. pwo0 * 4 pwc 0 signal output pin. * 4 34 33 41 p10 c general-purpose i/o ports. int0 can be used as interrupt request input channels 0. input is en- abled when 1 is set in en0 in standby mode. dtti0 rto0 to 5 pins for fixed-level input. this function is enabled when the waveform generator enables its input bits. 35 34 42 p11 c general-purpose i/o ports. int1 can be used as interrupt request input channels 1. input is en- abled when 1 is set in en1 in standby mode. 36 35 43 p12 c general-purpose i/o ports. int2 can be used as interrupt request input channels 2. input is en- abled when 1 is set in en2 in standby mode. dtti1 * 4 opt0 to 5 pins for fixed-level input. this function is enabled when the waveform sequencer enables its input bit. * 4 37 to 38 36 to 37 44 to 45 p13 to p14 c general-purpose i/o ports. int3 to int4 can be used as interrupt request input channels 3 to 4. input is enabled when 1 is set in en3 to en4 in standby mode. 39 38 46 p15 c general-purpose i/o ports. int5 can be used as interrupt request input channel 5. input is en- abled when 1 is set in en5 in standby mode. tin0 external clock input pin for reload timer 0. mb90460 series 10 pin no. pin name i/o circuit function qfp- m06* 2 lqfp- m09* 1 sdip* 3 40 39 47 p16 c general-purpose i/o ports. int6 can be used as interrupt request input channels 6. input is en- abled when 1 is set in en6 in standby mode. to0 event output pin for reload timer 0. 41 40 48 p17 c general-purpose i/o ports. frck external clock input pin for free-running timer. 42 41 49 p20 f general-purpose i/o ports. tin1 external clock input pin for reload timer 1. 43 42 50 p21 f general-purpose i/o ports. to1 event output pin for reload timer 1. 44 43 51 p22 f general-purpose i/o ports. pwi1 pwc 1 signal input pin. 45 44 52 p23 f general-purpose i/o ports. pwo1 pwc 1 signal output pin. 46 to 49 45 to 48 53 to 56 p24 to p27 f general-purpose i/o ports. in0 to in3 trigger input pins for input capture channels 0 to 3. when input capture channels 0 to 3 are used for input operation, these pins are enabled as required and must not be used for any other i/p. 51 to 56 50 to 55 58 to 63 p30 to p35 g general-purpose i/o ports. rto0 (u) to rto5 (z) waveform generator output pins. these pins output the wave- forms specified at the waveform generator. output is generated when waveform generator output is enabled. (u) to (z) show the coils that control 3-phase motor. 59 58 2 p36 h general-purpose i/o ports. ppg1 * 4 output pins for ppg channels 1. this function is enabled when ppg channels 1 enable output. * 4 60 59 3 p37 h general-purpose i/o ports. ppg0 output pins for ppg channels 0. this function is enabled when ppg channels 0 enable output. 61 60 4 p40 f general-purpose i/o ports. sin0 serial data input pin for uart channel 0. while uart channel 0 is operating for input, the input of this pin is used as required and must not be used for any other input. 62 61 5 p41 f general-purpose i/o ports. sot0 serial data output pin for uart channel 0. this function is en- abled when uart channel 0 enables data output. mb90460 series 11 (continued) (continued) (continued) pin no. pin name i/o circuit function qfp- m06* 2 lqfp- m09* 1 sdip* 3 63 62 6 p42 f general-purpose i/o ports. sck0 serial clock i/o pin for uart channel 0. this function is enabled when uart channel 0 enables clock output. 64 63 7 p43 f general-purpose i/o ports. sni0 * 4 trigger input pins for position detection of the waveform se- quencer. when this pin is used for input operation, it is enabled as required and must not be used for any other i/p. * 4 1648 p44 f general-purpose i/o ports. sni1 * 4 trigger input pins for position detection of the multi-pulse gener- ator. when this pin is used for input operation, it is enabled as required and must not be used for any other i/p. * 4 219 p45 f general-purpose i/o ports. sni2 * 4 trigger input pins for position detection of the multi-pulse gener- ator. when this pin is used for input operation, it is enabled as required and must not be used for any other i/p. * 4 3210 p46 f general-purpose i/o ports. ppg2 output pins for ppg channel 2. this function is enabled when ppg channel 2 enables output. 4 to 11 3 to 10 11 to 18 p50 to p57 i general-purpose i/o ports. an0 to an7 a/d converter analog input pins. this function is enabled when the analog input specification is enabled. (ader) . 12 11 19 av cc ? v cc power input pin for analog circuits. 13 12 20 avr ? reference voltage ( + ) input pin for the a/d converter. this volt- age must not exceed v cc and av cc . reference voltage ( - ) is fixed to av ss . 14 13 21 av ss ? v ss power input pin for analog circuits. 15 14 22 p60 f general-purpose i/o ports. sin1 serial data input pin for uart channel 1. while uart channel 1 is operating for input, the input of this pin is used as required and must not be used for any other in-put. 16 15 23 p61 f general-purpose i/o ports. sot1 serial data output pin for uart channel 1. this function is en- abled when uart channel 1 enables data output. mb90460 series 12 (continued) *1 : fpt-64p-m09 *2 : fpt-64p-m06 *3 : dip-64p-m01 *4 : mb90v460, mb90f462, mb90462 only. they do not exist on mb90467, because there are not pwc (ch 0) , 16-bit ppg (ch 1) and waveform sequencer. pin no. pin name i/o circuit function qfp- m06* 2 lqfp- m09* 1 sdip* 3 17 16 24 p62 f general-purpose i/o port. sck1 serial clock i/o pin for uart channel 1. this function is enabled when uart channel 1 enables clock output. 18 17 25 p63 f general-purpose i/o port. int7 usable as interrupt request input channel 7. input is enabled when 1 is set in en7 in standby mode. 19 18 26 md0 j input pin for operation mode specification. connect this pin di- rectly to v cc or v ss . 21, 22 20, 21 28, 29 md1, md2 j input pin for operation mode specification. connect this pin di- rectly to v cc or v ss . 25, 50 24, 49 32, 57 v ss ? power (0 v) input pin. 57 56 64 v cc ? power (5 v) input pin. 58 57 1 c ? capacity pin for power stabilization. please connect to an ap- proximately 0.1 m f ceramic capacitor. mb90460 series 13 n n n n i/o circuit type (continued) classification type remarks a main clock (main clock crystal oscillator) ? at an oscillation feedback resistor of approximately 1 m w b ? hysteresis input ? pull-up resistor approximately 50 k w c ? cmos output ? hysteresis input ? selectable pull-up resistor approximately 50 k w ?i ol = 4 ma ? standby control available d ? cmos output ? cmos input ? selectable pull-up resistor approximately 50 k w ? standby control available ?i ol = 12 ma x1 xout x0 n-ch p-ch n-ch p-ch standby mode control r r pout p-ch pull up control hysteresis input standby mode control p-ch n-ch nout r pout p-ch pull up control cmos input standby mode control p-ch n-ch nout mb90460 series 14 (continued) classification type remarks e ? cmos output ? cmos input ? selectable pull-up resistor approximately 50 k w ? standby control available ?i ol = 4 ma f ? cmos output ? hysteresis input ? standby control available ?i ol = 4 ma g ? cmos output ? cmos input ? standby control available ?i ol = 12 ma h ? cmos output ? cmos input ? standby control available ?i ol = 4 ma r pout p-ch pull up control cmos input standby mode control p-ch n-ch nout pout hysteresis input standby mode control p-ch n-ch nout pout cmos input standby mode control p-ch n-ch nout pout cmos input standby mode control p-ch n-ch nout mb90460 series 15 (continued) classification type remarks i ? cmos output ? cmos input ? analog input ?i ol = 4 ma j ? hysteresis input pout cmos input analog input control analog input p-ch n-ch nout mb90460 series 16 n n n n handling devices 1. preventing latchup cmos ics may cause latchup in the following situations : ? when a voltage higher than v cc or lower than v ss is applied to input or output pins. ? when a voltage exceeding the rating is applied between v cc and v ss . ? when av cc power is supplied prior to the v cc voltage. if latchup occurs, the power supply current increases rapidly, sometimes resulting in thermal breakdown of the device. use meticulous care not to let it occur. for the same reason, also be careful not to let the analog power-supply voltage exceed the digital power-supply voltage. 2. handling unused input pins unused input pins left open may cause abnormal operation, or latch-up leading to permanent damage. unused input pins should be pulled up or pulled down through at least 2 k w resistance. unused input/output pins may be left open in the output state, but if such pins are in the input state they should be handled in the same way as input pins. 3. use of the external clock when the device uses an external clock, drive only the x0 pin while leaving the x1 pin open (see the illustration below) . 4. power supply pins (v cc /v ss ) in products with multiple v cc or v ss pins, the pins of a same potential are internally connected in the device to avoid abnormal operations including latch-up. however, connect the pins external power and ground lines to lower the electro-magnetic emission level to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total current rating. make sure to connect v cc and v ss pins via the lowest impedance to power lines. it is recommended to provide a bypass capacitor of around 0.1 m f between v cc and v ss pins near the device. 5. crystal oscillator circuit noise around x0 or x1 pins may cause abnormal operations. make sure to provide bypass capacitors via the shortest distance from x0, x1 pins, crystal oscillator (or ceramic resonator) and ground lines, and make sure, to the utmost effort, that lines of oscillation circuit not cross the lines of other circuits. it is highly recommended to provide a printed circuit board art work surrounding x0 and x1 pins with the ground area for stabilizing the operation. 6. turning-on sequence of power supply to a/d converter and analog inputs make sure to turn on the a/d converter power supply (av cc , av ss , avr) and analog inputs (an0 to an7) after turning-on the digital power supply (v cc ) . turn-off the digital power after turning off the a/d converter supply and analog inputs. in this case, make sure that the voltage of avr dose not exceed av cc (turning on/off the analog and digital power supplies simultaneously is acceptable) . x0 x1 open mb90460 series mb90460 series 17 7. connection of unused pins of a/d converter connect unused pin of a/d converter to av cc = v cc , av ss = avr = v ss . 8. n.c. pin the n.c. (internally connected) pin must be opened for use. 9. notes on energization to prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at 50 m s or more. 10. initialization in the device, there are internal registers which are initialized only by a power-on reset. to initialize these registers, please turn on the power again. 11. return from standby state if the power-supply voltage goes below the standby ram holding voltage in the standby state, the device may fail to return from the standby state. in this case, reset the device via the external reset pin to return to the normal state. mb90460 series 18 n n n n block diagram x0 x1 rst p11/int1 p40/sin0 p41/sot0 p42/sck0 p36/ppg1 *2 p15/int5/tin0 p16/int6/to0 p00/opt0 *2 p01/opt1 *2 p02/opt2 *2 p03/opt3 *2 p04/opt4 *2 p05/opt5 *2 p06/pwi0 *2 p07/pwo0 *2 p46/ppg2 p12/int2/dtti1 *2 p43/sni0 *2 to p45/sni2 *2 p13/int3 to p14/int4 2 3 clock control circuit reset circuit (watch-dog timer) interrupt controller dtp/external interrupt uart (ch0) 16-bit ppg (ch1) 16-bit reload timer (ch0) waveform sequencer multi-pulse generator 3 8 pwc (ch0) 16-bit ppg (ch2) cmos i/o port 0, 1, 3, 4 ram rom rom correction rom mirroring f 2 mc-16lx bus cpu f 2 mc-16lx series core other pins v ss 2, v cc 1, md0-2, c timebase timer delayed interrupt generator multi-functional timer 44 16-bit ppg (ch0) 16-bit input capture (ch0/1/2/3) 16-bit free-run timer 16-bit output compare (ch0 to 5) waveform generator 16-bit reload timer (ch1) pwc (ch1) uart (ch1) cmos i/o port 1, 2, 3, 6 cmos i/o port 5 a/d converter (8/10 bit) p37/ppg0 p17/frck p30/rto0 (u) p31/rto1 (x) p32/rto2 (v) p33/rto3 (y) p34/rto4 (w) p35/rto5 (z) p10/int0/dtti0 p20/tin1 p22/pwi1 p23/pwo1 p60/sin1 p61/sot1 p62/sck1 p63/int7 p50/an0 p51/an1 p52/an2 p53/an3 p54/an4 p55/an5 p56/an6 p57/an7 av cc avr av ss p21/to1 p24/in0 to p27/in3 8 *1 *1 *1 *2 note : p00 to p07 (8 channels) : with registers that can be used as input pull-up resistors p10 to p17 (8 channels) : with registers that can be used as input pull-up resistors *1: only mb90v460, mb90f462 and mb90462 have pwc (ch 0) , 16-bit ppg (ch 1) and waveform sequencer. they do not exist on mb90467. *2: the multi-pulse generator function can be used only by mb90v460, mb90f462 and mb90462. this function can not be used by mb90467. mb90460 series 19 n n n n memory map note : the rom data of bank ff is reflected in the upper address of bank 00, realizing effective use of the c compiler small model. the lower 16-bit is assigned to the same address, enabling reference of the table on the rom without stating far. for example, if an attempt has been made to access 00c000 h , the contents of the rom at ffc000 h are accessed actually. since the rom area of the ff bank exceeds 48 kbytes, the whole area cannot be reflected in the image for the 00 bank. the rom data at ff4000 h to ffffff h looks, therefore, as if it were the image for 004000 h to 00ffff h . thus, it is recommended that the rom data table be stored in the area of ff4000 h to ffffff h . ffffff h address #1 address #2 address #3 fc0000 h 010000 h 004000 h 003fe0 h 000100 h 0000c0 h 000000 h rom area register rom area (ff bank image) peripheral area peripheral area ram area : internal access memory : access not allowed in single chip mode the mirror function is supported parts no. address#1 address#2 address#3 mb90462/467 ff0000 h 004000 h 000900 h mb90f462 ff0000 h 004000 h 000900 h mb90v460 (ff0000 h ) 004000 h 002100 h mb90460 series 20 n n n n i/o map (continued) address abbrevia- tion register byte access word access resource name initial value 000000 h pdr0 port 0 data register r/w r/w port 0 xxxxxxxx b 000001 h pdr1 port 1 data register r/w r/w port 1 xxxxxxxx b 000002 h pdr2 port 2 data register r/w r/w port 2 xxxxxxxx b 000003 h pdr3 port 3 data register r/w r/w port 3 xxxxxxxx b 000004 h pdr4 port 4 data register r/w r/w port 4 -xxxxxxx b 000005 h pdr5 port 5 data register r/w r/w port 5 xxxxxxxx b 000006 h pdr6 port 6 data register r/w r/w port 6 ----xxxx b 000007 h prohibited area 000008 h pwcsl0 pwc control status register ch0 r/w r/w pwc timer (ch0) 00000000 b 000009 h pwcsh0 r/w r/w 00000000 b 00000a h pwc0 pwc data buffer register ch0 ? r/w xxxxxxxx b 00000b h xxxxxxxx b 00000c h div0 divide ratio control register ch0 r/w r/w ------00 b 00000d h to 0f h prohibited area 000010 h ddr0 port 0 direction register r/w r/w port 0 00000000 b 000011 h ddr1 port 1 direction register r/w r/w port 1 00000000 b 000012 h ddr2 port 2 direction register r/w r/w port 2 00000000 b 000013 h ddr3 port 3 direction register r/w r/w port 3 00000000 b 000014 h ddr4 port 4 direction register r/w r/w port 4 -0000000 b 000015 h ddr5 port 5 direction register r/w r/w port 5 00000000 b 000016 h ddr6 port 6 direction register r/w r/w port 6 ----0000 b 000017 h ader analog input enable register r/w r/w port 5, a/d 11111111 b 000018 h prohibited area 000019 h cdcr0 clock division control register 0 r/w r/w communication prescaler 0 0---0000 b 00001a h prohibited area 00001b h cdcr1 clock division control register 1 r/w r/w communication prescaler 1 0---0000 b 00001c h rdr0 port 0 pull-up resistor setting register r/w r/w port 0 00000000 b 00001d h rdr1 port 1 pull-up resistor setting register r/w r/w port 1 00000000 b 00001e h to 1f h prohibited area mb90460 series 21 (continued) address abbrevia- tion register byte access word access resource name initial value 000020 h smr0 serial mode register 0 r/w r/w uart0 00000000 b 000021 h scr0 serial control register 0 r/w r/w 00000100 b 000022 h sidr0 / sodr0 input data register 0 / output data register 0 r/w r/w xxxxxxxx b 000023 h ssr0 serial status register 0 r/w r/w 00001000 b 000024 h smr1 serial mode register 1 r/w r/w uart1 00000000 b 000025 h scr1 serial control register 1 r/w r/w 00000100 b 000026 h sidr1 / sodr1 input data register 1 / output data register 1 r/w r/w xxxxxxxx b 000027 h ssr1 status register 1 r/w r/w 00001000 b 000028 h pwcsl1 pwc control status register ch1 r/w r/w pwc timer (ch1) 00000000 b 000029 h pwcsh1 r/w r/w 00000000 b 00002a h pwc1 pwc data buffer register ch1 ? r/w xxxxxxxx b 00002b h xxxxxxxx b 00002c h div1 divide ratio control register ch1 r/w r/w ------00 b 00002d h to 2f h prohibited area 000030 h enir interrupt / dtp enable register r/w r/w dtp/external interrupt 00000000 b 000031 h eirr interrupt / dtp cause register r/w r/w xxxxxxxx b 000032 h elvrl request level setting register (lower byte) r/w r/w 00000000 b 000033 h elvrh request level setting register (higher byte) r/w r/w 00000000 b 000034 h adcs0 a/d control status register 0 r/w r/w 8/10-bit a/d converter 00000000 b 000035 h adcs1 a/d control status register 1 r/w r/w 00000000 b 000036 h adcr0 a/d data register 0 r r xxxxxxxx b 000037 h adcr1 a/d data register 1 r/w r/w 00000-xx b 000038 h pdcr0 ppg0 down counter register ? r 16-bit ppg timer (ch0) 11111111 b 000039 h 11111111 b 00003a h pcsr0 ppg0 period setting register ? w xxxxxxxx b 00003b h xxxxxxxx b 00003c h pdut0 ppg0 duty setting register ? w xxxxxxxx b 00003d h xxxxxxxx b 00003e h pcntl0 ppg0 control status register r/w r/w --000000 b 00003f h pcnth0 r/w r/w 00000000 b mb90460 series 22 (continued) address abbrevia- tion register byte access word access resource name initial value 000040 h pdcr1 ppg1 down counter register ? r 16-bit ppg timer (ch1) 11111111 b 000041 h 11111111 b 000042 h pcsr1 ppg1 period setting register ? w xxxxxxxx b 000043 h xxxxxxxx b 000044 h pdut1 ppg1 duty setting register ? w xxxxxxxx b 000045 h xxxxxxxx b 000046 h pcntl1 ppg1 control status register r/w r/w --000000 b 000047 h pcnth1 r/w r/w 00000000 b 000048 h pdcr2 ppg2 down counter register ? r 16-bit ppg timer (ch2) 11111111 b 000049 h 11111111 b 00004a h pcsr2 ppg2 period setting register ? w xxxxxxxx b 00004b h xxxxxxxx b 00004c h pdut2 ppg2 duty setting register ? w xxxxxxxx b 00004d h xxxxxxxx b 00004e h pcntl2 ppg2 control status register r/w r/w --000000 b 00004f h pcnth2 r/w r/w 00000000 b 000050 h tmrr0 16-bit timer register 0 ? r/w waveform generator xxxxxxxx b 000051 h xxxxxxxx b 000052 h tmrr1 16-bit timer register 1 ? r/w xxxxxxxx b 000053 h xxxxxxxx b 000054 h tmrr2 16-bit timer register 2 ? r/w xxxxxxxx b 000055 h xxxxxxxx b 000056 h dtcr0 16-bit timer control register 0 r/w r/w 00000000 b 000057 h dtcr1 16-bit timer control register 1 r/w r/w 00000000 b 000058 h dtcr2 16-bit timer control register 2 r/w r/w 00000000 b 000059 h sigcr waveform control register r/w r/w 00000000 b 00005a h cpclrb / cpclr compare clear buffer register / compare clear register (lower) ? r/w 16-bit free-running timer 11111111 b 00005b h 11111111 b 00005c h tcdt timer data register (lower) ? r/w 00000000 b 00005d h 00000000 b 00005e h tccsl timer control status register (lower) r/w r/w 00000000 b 00005f h tccsh timer control status register (upper) r/w r/w -0000000 b mb90460 series 23 (continued) address abbrevia- tion register byte access word access resource name initial value 000060 h ipcp0 input capture data register ch0 ? r 16-bit input capture (ch0 to ch3) xxxxxxxx b 000061 h xxxxxxxx b 000062 h ipcp1 input capture data register ch1 ? r xxxxxxxx b 000063 h xxxxxxxx b 000064 h ipcp2 input capture data register ch2 ? r xxxxxxxx b 000065 h xxxxxxxx b 000066 h ipcp3 input capture data register ch3 ? r xxxxxxxx b 000067 h xxxxxxxx b 000068 h picsl01 ppg output control / input capture control status register 01 (lower) r/w r/w 00000000 b 000069 h picsh01 ppg output control / input capture control status register 01 (upper) r/w r/w 00000000 b 00006a h icsl23 input capture control status register 23 (lower) r/w r/w 00000000 b 00006b h icsh23 input capture control status register 23 (upper) r r ------00 b 00006c h to 6e h prohibited area 00006f h romm rom mirroring function selection register ww rom mirroring function -------1 b 000070 h occpb0/ occp0 output compare buffer register / output compare register 0 ? r/w output compare (ch0 to ch5) xxxxxxxx b 000071 h xxxxxxxx b 000072 h occpb1/ occp1 output compare buffer register / output compare register 1 ? r/w xxxxxxxx b 000073 h xxxxxxxx b 000074 h occpb2/ occp2 output compare buffer register / output compare register 2 ? r/w xxxxxxxx b 000075 h xxxxxxxx b 000076 h occpb3/ occp3 output compare buffer register / output compare register 3 ? r/w xxxxxxxx b 000077 h xxxxxxxx b 000078 h occpb4/ occp4 output compare buffer register / output compare register 4 ? r/w xxxxxxxx b 000079 h xxxxxxxx b 00007a h occpb5/ occp5 output compare buffer register / output compare register 5 ? r/w xxxxxxxx b 00007b h xxxxxxxx b mb90460 series 24 (continued) address abbrevia- tion register byte access word access resource name initial value 00007c h ocs0 compare control register 0 r/w r/w output compare (ch0 to ch5) 00000000 b 00007d h ocs1 compare control register 1 r/w r/w -0000000 b 00007e h ocs2 compare control register 2 r/w r/w 00000000 b 00007f h ocs3 compare control register 3 r/w r/w -0000000 b 000080 h ocs4 compare control register 4 r/w r/w 00000000 b 000081 h ocs5 compare control register 5 r/w r/w -0000000 b 000082 h tmcsrl0 timer control status register ch0 (lower) r/w r/w 16-bit reload timer (ch0) 00000000 b 000083 h tmcsrh0 timer control status register ch0 (upper) r/w r/w ----0000 b 000084 h tmr0 / tmrd0 16 bit timer register ch0 / 16-bit reload register ch0 ? r/w xxxxxxxx b 000085 h xxxxxxxx b 000086 h tmcsrl1 timer control status register ch1 (lower) r/w r/w 16-bit reload timer (ch1) 00000000 b 000087 h tmcsrh1 timer control status register ch1 (upper) r/w r/w ----0000 b 000088 h tmr1 / tmrd1 16 bit timer register ch1 / 16-bit reload register ch1 ? r/w xxxxxxxx b 000089 h xxxxxxxx b 00008a h opclr output control lower register r/w r/w waveform sequencer 00000000 b 00008b h opcur output control upper register r/w r/w 00000000 b 00008c h ipclr input control lower register r/w r/w 00000000 b 00008d h ipcur input control upper register r/w r/w 00000000 b 00008e h tcsr timer control status register r/w r/w 00000000 b 00008f h nccr noise cancellation control register r/w r/w 00000000 b 000090 h to 9d h prohibited area 00009e h pacsr program address detect control status register r/w r/w rom correction 00000000 b 00009f h dirr delayed interrupt cause / clear register r/w r/w delayed interrupt -------0 b 0000a0 h lpmcr low-power consumption mode register r/w r/w low-power consumption control register 00011000 b 0000a1 h ckscr clock selection register r/w r/w 11111100 b 0000a2 h to a7 h prohibited area 0000a8 h wdtc watchdog control register r/w r/w watchdog timer x-xxx111 b 0000a9 h tbtc timebase timer control register r/w r/w timebase timer 1--00100 b mb90460 series 25 (continued) address abbrevia- tion register byte access word access resource name initial value 0000aa h to ad h prohibited area 0000ae h fmcs flash memory control status register r/w r/w flash memory interface circuit 00010000 b 0000af h prohibited area 0000b0 h icr00 interrupt control register 00 r/w r/w interrupt controller 00000111 b 0000b1 h icr01 interrupt control register 01 r/w r/w 00000111 b 0000b2 h icr02 interrupt control register 02 r/w r/w 00000111 b 0000b3 h icr03 interrupt control register 03 r/w r/w 00000111 b 0000b4 h icr04 interrupt control register 04 r/w r/w 00000111 b 0000b5 h icr05 interrupt control register 05 r/w r/w 00000111 b 0000b6 h icr06 interrupt control register 06 r/w r/w 00000111 b 0000b7 h icr07 interrupt control register 07 r/w r/w 00000111 b 0000b8 h icr08 interrupt control register 08 r/w r/w 00000111 b 0000b9 h icr09 interrupt control register 09 r/w r/w 00000111 b 0000ba h icr10 interrupt control register 10 r/w r/w 00000111 b 0000bb h icr11 interrupt control register 11 r/w r/w 00000111 b 0000bc h icr12 interrupt control register 12 r/w r/w 00000111 b 0000bd h icr13 interrupt control register 13 r/w r/w 00000111 b 0000be h icr14 interrupt control register 14 r/w r/w 00000111 b 0000bf h icr15 interrupt control register 15 r/w r/w 00000111 b 0000c0 h to ff h external area 001ff0 h padr0l program address detection register 0 (lower byte) r/w r/w rom correction xxxxxxxx b 001ff1 h padr0m program address detection register 0 (middle byte) r/w r/w xxxxxxxx b 001ff2 h padr0h program address detection register 0 (higher byte) r/w r/w xxxxxxxx b 001ff3 h padr1l program address detection register 1 (lower byte) r/w r/w xxxxxxxx b 001ff4 h padr1m program address detection register 1 (middle byte) r/w r/w xxxxxxxx b 001ff5 h padr1h program address detection register 1 (higher byte) r/w r/w xxxxxxxx b mb90460 series 26 (continued) address abbrevia- tion register byte access word access resource name initial value 003fe0 h opdbr0 output data buffer register 0 ? r/w waveform sequencer 00000000 b 003fe1 h 00000000 b 003fe2 h opdbr1 output data buffer register 1 ? r/w 00000000 b 003fe3 h 00000000 b 003fe4 h opdbr2 output data buffer register 2 ? r/w 00000000 b 003fe5 h 00000000 b 003fe6 h opdbr3 output data buffer register 3 ? r/w 00000000 b 003fe7 h 00000000 b 003f78 h opdbr4 output data buffer register 4 ? r/w 00000000 b 003fe9 h 00000000 b 003fea h opdbr5 output data buffer register 5 ? r/w 00000000 b 003feb h 00000000 b 003fec h opebr6 output data buffer register 6 ? r/w 00000000 b 003fed h 00000000 b 003fee h opebr7 output data buffer register 7 ? r/w 00000000 b 003fef h 00000000 b 003ff0 h opebr8 output data buffer register 8 ? r/w 00000000 b 003ff1 h 00000000 b 003ff2 h opebr9 output data buffer register 9 ? r/w 00000000 b 003ff3 h 00000000 b 003ff4 h opebra output data buffer register a ? r/w 00000000 b 003ff5 h 00000000 b 003ff6 h opebrb output data buffer register b ? r/w 00000000 b 003ff7 h 00000000 b 003ff8 h opdr output data register ? r xxxxxxxx b 003ff9 h 0000xxxx b 003ffa h cpcr compare clear register ? r/w xxxxxxxx b 003ffb h xxxxxxxx b 003ffc h tmbr timer buffer register ? r 00000000 b 003ffd h 00000000 b 003ffe h to 003fff h prohibited area mb90460 series 27 ? meaning of abbreviations used for reading and writing ? explanation of initial values the instruction using io addressing e.g. mov a, io, is not supported for registers area 003fe0 h to 003fff h . note : for bits that is initialized by an reset operation, the initial value set by the reset operation is listed as an initial value. note that the values are different from reading results. for lpmcr/ckscr/wdtc, there are cases where initialization is performed or not performed, depending on the types of the reset. however, initial value for resets that initializes the value is listed. r/w : read and write enabled r : read only w : write only 0 : the bit is initialized to 0. 1 : the bit is initialized to 1. x : the initial value of the bit is undefined. - : the bit is not used. its initial value is undefined. mb90460 series 28 n n n n interrupt factors, interrupt vectors, interrupt control register (continued) interrupt cause ei 2 os support interrupt vector interrupt control register priority *2 number address icr address reset #08 08 h ffffdc h ?? high int9 instruction #09 09 h ffffd8 h ?? exception processing #10 0a h ffffd4 h ?? a/d converter conversion termination #11 0b h ffffd0 h icr00 0000b0 h *1 output compare channel 0 match #12 0c h ffffcc h end of measurement by pwc0 timer / pwc0 timer overflow #13 0d h ffffc8 h icr01 0000b1 h *1 16-bit ppg timer 0 #14 0e h ffffc4 h output compare channel 1 match #15 0f h ffffc0 h icr02 0000b2 h *1 16-bit ppg timer 1 #16 10 h ffffbc h output compare channel 2 match #17 11 h ffffb8 h icr03 0000b3 h *1 16-bit reload timer 1 underflow #18 12 h ffffb4 h output compare channel 3 match #19 13 h ffffb0 h icr04 0000b4 h *1 dtp/ext. interrupt channels 0/1 detection #20 14 h ffffac h dtti0 d output compare channel 4 match #21 15 h ffffa8 h icr05 0000b5 h *2 dtp/ext. interrupt channels 2/3 detection #22 16 h ffffa4 h dtti1 d output compare channel 5 match #23 17 h ffffa0 h icr06 0000b6 h *1 end of measurement by pwc1 timer / pwc1 timer overflow #24 18 h ffff9c h dtp/ext. interrupt channels 4/5 detection #25 19 h ffff98 h icr07 0000b7 h *1 waveform sequencer timer compare match / write timing #26 1a h ffff94 h dtp/ext. interrupt channels 6/7 detection #27 1b h ffff90 h icr08 0000b8 h *1 waveform sequencer position detect / compare interrupt #28 1c h ffff8c h waveform generator 16-bit timer 0/1/2 underflow d #29 1d h ffff88 h icr09 0000b9 h *1 16-bit reload timer 0 underflow #30 1e h ffff84 h 16-bit free-running timer zero detect d #31 1f h ffff80 h icr10 0000ba h *1 16-bit ppg timer 2 #32 20 h ffff7c h input capture channels 0/1 #33 21 h ffff78 h icr11 0000bb h *1 16-bit free-running timer compare clear d #34 22 h ffff74 h mb90460 series 29 (continued) : can be used and support the ei 2 os stop request. : can be used and interrupt request flag is cleared by ei 2 os interrupt clear signal. : cannot be used. d : usable when an interrupt cause that shares the icr is not used. interrupt cause ei2os support interrupt vector interrupt control register priority *2 number address icr address input capture channels 2/3 #35 23 h ffff70 h icr12 0000bc h *1 timebase timer d #36 24 h ffff6c h uart1 receive #37 25 h ffff68 h icr13 0000bd h *1 uart1 send d #38 26 h ffff64 h uart0 receive #39 27 h ffff60 h icr14 0000be h *1 uart0 send d #40 28 h ffff5c h flash memory status d #41 29 h ffff58 h icr15 0000bf h *1 delayed interrupt generator module d #42 2a h ffff54 h low mb90460 series 30 n n n n peripheral resources 1. low-power consumption control circuit the mb90460 series has the following cpu operating mode configured by selection of an operating clock and clock operation control. ? clock mode pll clock mode : a pll clock that is a multiple of the oscillation clock (hclk) frequency is used to operate the cpu and peripheral functions. main clock mode : the main clock, with a frequency one-half that of the oscillation clock (hclk) , is used to operate the cpu and peripheral functions. in main clock mode, the pll multiplier circuit is inactive. ? cpu intermittent operation mode cpu intermittent operation mode causes the cpu to operate intermittently, while high-speed clock pulses are supplied to peripheral functions, reducing power consumption. in cpu intermittent operation mode, intermittent clock pulses are only applied to the cpu when it is accessing a register, internal memory, a peripheral function, or an external unit. ? standby mode in standby mode, the low power consumption control circuit stops supplying the clock to the cpu (sleep mode) or the cpu and peripheral functions (timebase timer mode) , or stops the oscillation clock itself (stop mode) , reducing power consumption. ? pll sleep mode pll sleep mode is activated to stop the cpu operating clock when the microcontroller enters pll clock mode; other components continue to operate on the pll clock. ? main sleep mode main sleep mode is activated to stop the cpu operating clock when the microcontroller enters main clock mode; other components continue to operate on the main clock. ? pll timebase timer mode pll timebase timer mode causes microcontroller operation, with the exception of the oscillation clock, pll clock and timebase timer, to stop. all functions other than the timebase timer are deactivated. ? main timebase timer mode main timebase timer mode causes microcontroller operation, with the exception of the oscillation clock, main clock and the timebase timer, to stop. all functions other than the timebase timer are deactivated. ? stop mode stop mode causes the source oscillation to stop. all functions are deactivated. mb90460 series 31 block diagram resv mcm ws1 ws0 resv mcs cs1 cs0 stp pin pin pin slp spl rst tmd cg1 cpu intermittent operation selecter pin high impedance control circuit internal reset generation circuit cpu clock control circuit peripheral clock control circuit cg0 resv 2 2 x0 x1 rst rst release reset cancel interrupt clock generator low power mode control register (lpmcr) pin hi-z control internal reset cpu clock stop and sleep signals stop signal machine clock clock selector clock selection register (ckscr) timebase timer system clock generation circuit oscillation stabilization wait is passed peripheral clock oscillation stabilization wait interval selector select intermittent cycles standby control circuit pll multipiler circuit 1 2 3 4 divide- by-4 divide- by-4 divide- by-4 divide- by-2 divide- by-512 divide- by-2 main clock 3 mb90460 series 32 2. i/o ports (1) outline of i/o ports when a data register serving for control output is read, the data output from it as a control output is read regardless of the value in the direction register. note that, if a read-modify-write instruction (such as a bit set instruction) is used to preset output data in the data register when changing its setting from input to output, the data read is not the data register latched value but the input data from the pin. ports 0 to 4 and 6 are input/output ports which serve as inputs when the direction register value is 0 or as outputs when the value is 1. port 5 are input/output ports as other port when ader is 00 h . block diagram ? block diagram of port 0 pins (continued) rdr port data register (pdr) resource output enable pull-up resistor about 50 k w standby control (spl = 1) pdr read pdr write ddr write ddr read port data direction register (ddr) internal data bus output latch pin resource output direction latch direct resource input mb90460 series 33 ? block diagram of port 1 pins ? block diagram of port 2 pins (continued) rdr port data register (pdr) resource output enable pull-up resistor about 50 k w standby control (spl = 1) pdr read pdr write ddr write ddr read port data direction register (ddr) internal data bus output latch pin resource output direction latch resource input port data register (pdr) resource output enable standby control (spl = 1) pdr read pdr write ddr write ddr read port data direction register (ddr) internal data bus output latch pin resource output direction latch resource input mb90460 series 34 ? block diagram of port 3 pins ? block diagram of port 4 pins (continued) port data register (pdr) resource output enable standby control (spl = 1) pdr read pdr write ddr write ddr read port data direction register (ddr) internal data bus output latch pin resource output direction latch port data register (pdr) resource output enable standby control (spl = 1) pdr read pdr write ddr write ddr read port data direction register (ddr) internal data bus output latch pin resource output direction latch resource input mb90460 series 35 (continued) ? block diagram of port 5 pins ? block diagram of port 6 pins ader port data register (pdr) standby control (spl = 1) pdr read pdr write ddr write ddr read port data direction register (ddr) internal data bus output latch pin direction latch analog input port data register (pdr) resource output enable standby control (spl = 1) pdr read pdr write ddr write ddr read port data direction register (ddr) internal data bus output latch pin resource output external interrupt enable direction latch resource input mb90460 series 36 3. timebase timer the timebase timer is an 18-bit free-running counter (timebase counter) that counts up in synchronization to the internal count clock (main oscillator clock divided by 2) . features of timebase timer : ? interrupt generated when counter overflow ?ei 2 os supported ? interval timer function : an interrupt generated at four different time intervals ? clock supply function : four different clocks can be selected as a watchdog timers count clock supply clock for oscillation stabilization block diagram ??? tbie tbof tbr tbc1 tbc0 2 1 2 2 2 3 2 8 2 9 2 10 2 11 2 12 2 13 2 14 2 15 2 16 2 18 2 17 of counter clear circuit interval timer selector of of of timebase timer counter counter clear timebase timer interrupt signal #36 (24 h )* 2 tbof clear tbof set to watchdog timer to the oscillation setting time selector in the clock control section divide-by -two hclk power-on reset stop mode start ckscr : mcs = 1 to 0 * 1 timebase timer interrpt register (tbtc) of : overflow hclk : oscillation clock *1 : switching of the machine clock from the oscillation clock to the pll clock *2 : interrupt number mb90460 series 37 4. watchdog timer the watchdog timer is a 2-bit counter that uses the timebase timers supply clock as the count clock. after activation, if the watchdog timer is not cleared within a given period, the cpu will be reset. ? features of watchdog timer : reset cpu at four different time intervals status bits to indicate the reset causes block diagram ponr stbr wrst erst srst wte wt1 wt0 2 1 2 2 2 8 2 9 2 10 2 11 2 12 2 13 2 14 2 15 2 16 2 17 2 18 2 4 counter clear control circuit count clock selector 2-bit counter watchdog reset generator one-half of hclk watchdog timer control register (wdtc) watchdog timer activation with clr to the internal reset generator clr clr clear (timebase timer counter) over- flow start of sleep mode start of hold status mode start of stop mode hclk : oscillation clock mb90460 series 38 5. 16 bit reload timer ( 2) the 16-bit reload timer provides two operating mode, internal clock mode and event count mode. in each operating mode, the 16-bit down counter can be reloaded (reload mode) or stopped when underflow (one-shot mode) . output pins to1 - to0 are able to output different waveform accroding to the counter operating mode. to1 - to0 toggles when counter underflow if counter is operated as reload mode. to1 - to0 output specified level (h or l) when counter is counting if the counter is in one-shot mode. features of the 16 bit reload timer : ? interrupt generated when timer underflow ?ei 2 os supported ? internal clock operating mode : three internal count clocks can be selected counter can be activated by software or exteranl trigger (singal at tin1 - tin0 pin) counter can be reloaded or stopped when underflow after activated ? event count operating mode : counter counts down by one when specified edge at tin1 - tin0 pin counter can be reloaded or stopped when underflow mb90460 series 39 block diagram tmrd0* 1 mb90460 series 40 6. 16-bit ppg timer ( 3 ) the 16-bit ppg timer consists of a 16-bit down counter, prescaler, 16-bit period setting buffer register, 16-bit duty setting buffer register, 16-bit control register and a ppg output pin. this module can be used to output pulses synchronized by software trigger or gate signal from multi-functional timer, refer to multi-functional timer features of 16-bit ppg timer : ? two operating mode : pwm and one-shot ? 8 types of counter operation clock ( f , f /2, f /4, f /8, f /16, f /32, f /64, f /128) can be selected ? interrupt generated when trigger signal arrived, or counter borrow, or change of ppg output ?ei 2 os supported block diagram prescaler cks2 cks1 cks0 period setting buffer register 0/1/2 duty setting buffer register 0/1/2 duty setting register 0/1/2 period setting register 0/1/2 1/1 1/2 1/4 1/8 1/16 1/32 1/64 1/128 machine clock f down counter register 0/1/2 gate-from multi-functional timer (for ppg ch. 0 only) edge detection clk load borrow start stop 16-bit down counter comparator sq r mdse pgms osel poen pin p37/ppg0 or p36/ppg1 or p46/ppg2 ppg0 (multi-functional timer) or ppg1 (multi-pulse generator) or ppg2 interrupt selection interrupt #14/#16/#32 irs1 irs0 irqf iren f 2 mc-16lx bus (for ppg ch. 1 & 2) stgr cnte rtrg mb90460 series 41 7. multi-functional timer the 16-bit multi-functional timer module consists of one 16-bit free-running timer, four input capture circuits, six output comparators and one channel of 16-bit ppg timer. this module allows six independent waveforms generated by ppg timer or waveform generator to be outputted. with the 16-bit free-run timer and the input capture circuit, a input pulse width measurement and external clock cycle measurement can be done. (1) 16-bit free-running timer (1 channel) ? the 16-bit free-running timer consists of a 16-bit up/up-down counter, control register, 16-bit compare clear register (with buffer register) and a prescaler. ? 8 types of counter operation clock ( f , f /2, f /4, f /8, f /16, f /32, f /64, f /128) can be selected. ( f is the machine clock) ? two types of interrupt causes : - compare clear interrupt is generated when there is a comparing match with compare clear register and 16- bit free-run timer. - zero detection interrupt is generated while 16-bit free-running timer is detected as zero in count value. ?ei 2 os supported ? the compare clear register has a selectable buffer register, into which data is written for transfer to the compare clear register. when the timer is stopped, transfer occurs immediately when the data is written to the buffer. when the timer is operation, data transfer from the buffer occurs when the timer value is detected to be zero. ? reset, software clear, compare match with compare clear register in up-count mode will reset the counter value to 0000 h . ? supply clock to output compare module : the prescaler ouptut is acted as the count clock of the output compare. (2) output compare module (6 channels) ? the output compare module consists of six 16-bit compare registers (with selectable buffer register) , compare output latch and compare control registers. an interrupt is generated and output level is inverted when the value of 16-bit free-running timer and compare register are matched. ? 6 compare registers can be operated independently. ? output pins and interrupt flag are corresponding to each compare register. ? inverts output pins by using 2 compare registers together. 2 compare registers can be paired to control the output pins. ? setting the initial value for each output pin is possible. ? interrupt generated when there is a comparing match with output compare register and 16 bit free-run timer ?ei 2 os supported (3) input capture module (4 channels) input capture consists of 4 independent external input pins, the corresponding capture register and capture control register. by detecting any edge of the input signal from the external pin, the value of the 16-bit free- running timer can be stored in the capture register and an interrupt is generated simultaneously. ? operation synchronized with the 16-bit free-run timers count clock. ? 3 types of trigger edge (rising edge, falling edge and both edge) of the external input signal can be selected and there is indication bit to show the trigger edge is rising or falling. ? 4 input captures can be operated independently. ? two independent interrupts are generated when detecting a valid edge from external input. ?ei 2 os supported (4) 16-bit ppg timer ( 1) the 16-bit ppg timer 0 is used to provide a ppg signal for waveform generator. mb90460 series 42 (5) waveform generator module the waveform generator consists of three 16-bit timer registers, three timer control registers and 16-bit waveform control register. with waveform generator, it is possible to generate real time output, 16-bit ppg waveform output, non-overlap 3-phase waveform output for inverter control and dc chopper waveform output. ? it is possible to generate a non-overlap waveform output based on dead-time of 16-bit timer. (dead-time timer function) ? it is possible to generate a non-overlap waveform output when realtime output is operated in 2-channel mode. (dead-time timer function) ? by detecting realtime output compare match, gate signal of the ppg timer operation will be generated to start or stop ppg timer operation. (gate function) ? when a match is detected by realtime output compare, the 16-bit timer is activated. the ppg timer can be started or stopped easily by generating a gate signal for ppg operation until the 16-bit timer stops. (gate function) ? forced to stop output waveform using dtti0 pin input ? interrupt generated when dtti0 active or 16-bit tmer underflow ?ei 2 os supported ? mcu to 3-phase motor interface circuit rto0 (u) , rto2 (v) , rto4 (w) are called upper arm. rto1 (x) , rto3 (y) , rto5 (z) are called lower arm. rto0 (u) and rto1 (x) are called non-overlapping output pair. rto2 (v) and rto3 (y) are called non-overlapping output pair. rto4 (w) and rto5 (z) are called non-overlapping output pair. (u) , (v) , (w) are the 3-phase coil connection. rto4(w) (v) rto5(z) (w) rto2(v) (u) rto3(y) rto0(u) rto1(x) v cc mb90460 series 43 ? 3-phase motor coil connection circuit (u) (v) (w) (v) (w) (u) star connection circuit delta connection circuit mb90460 series 44 block diagram ? block diagram of multi-functional timer (continued) real time i/o interrupt#12 interrupt#15 interrupt#17 interrupt#19 interrupt#21 interrupt#23 output compare 0 output compare 1 output compare 2 output compare 3 output compare 4 output compare 5 rt0 to 5 16-bit output compare buffer transfer counter value 16-bit free- running timer interrupt#31 interrupt#34 a/d trigger a/d trigger exck zero detect compare clear input capture 0/1 input capture 2/3 counter value interrupt #33 interrupt #35 16-bit input capture in0 in1 in2 in3 rt0 to 5 waveform generator rto0 rto1 rto2 rto3 rto4 rto5 dtti ppg0 ppg0 gate gate interrupt#29 16-bit timer 0/1/2 underflow interrupt#20 dtti0 falling edge detect pin pin pin pin pin pin pin pin pin pin pin pin p24/in0 p17/frck p10/int0/dtti0 p35/rto5 (z) p34/rto4 (w) p33/rto3 (y) p32/rto2 (v) p31/rto1 (x) p30/rto0 (u) p25/in1 p26/in2 p27/in3 f 2 mc-16lx bus mb90460 series 45 ? block diagram of 16-bit free-running timer (continued) f 2 mc-16lx bus f prescaler stop mode sclr clk2 clk1 clk0 zero detect circuit zero detect (to output compare) stop up/ up-down clr 16-bit free-running timer ck transfer 16-bit compare clear register compare circuit to input capture & output compare compare clear match (to output compare) 16-bit compare clear buffer register selector i0 i1 o mask circuit selector selector i0 i1 i0 i1 o o selector i0 i1 o msi2 msi1 msi0 iclr icre irqzf irqze a/d trigger interrupt #34 (22 h ) interrupt #31 (1f h ) mb90460 series 46 ? block diagram of 16-bit output compare ? block diagram of 16-bit input capture (continued) buf0 buf1 bts0 bts1 selector selector o o i0 i1 i0 i1 zero detect from free-running timer compare clear match from free-running timer count value from free-running timer compare buffer register 0/2/4 compare register 0/2/4 compare register 1/3/5 compare circuit compare circuit compare buffer register 1/3/5 transfer transfer cmod f 2 mc-16lx bus tq tq rt0/2/4 (waveform generator) rt1/3/5 (waveform generator) iop1 iop0 ioe1 ioe0 interrupt #12, #17, #21 #15, #19, #23 count value from free-running timer capture register 0/2 capture register 1/3 f 2 mc-16lx bus interrupt #33, #35 #33, #35 in0/2 in1/3 edge detect edge detect eg11 eg10 eg01 eg00 iei1 iei0 icp0 icp1 ice0 ice1 mb90460 series 47 (continued) ? block diagram of waveform generator f 2 mc-16lx bus f divider dck2 dck1 dck0 nrsl dtif dtie nws1 nws0 sigcr dtti0 noise cancellation dtti0 control circuit gate 0/1 gate (to ppg0) to0 to1 to2 to3 to4 to5 u x v y w z waveform control selector output control output control output control rto0 (u) rto1 (x) rto2 (v) rto3 (y) rto4 (w) rto5 (z) selector selector selector gate 4/5 gate 2/3 dead time generator dead time generator dead time generator selector selector waveform control waveform control picsh01 dtcr0 rt0 rt1 rt2 rt3 rt4 rt5 16-bit timer 0 16-bit timer register 0 16-bit timer register 1 16-bit timer register 2 compare circuit 16-bit timer 1 compare circuit 16-bit timer 2 compare circuit dtcr1 dtcr2 picsh01 picsh01 ppg0 tmd2 tmd1 tmd0 gten1 gten0 tmd2 tmd1 tmd0 gten1 gten0 tmd2 tmd1 tmd0 gten1 gten0 pgen5 pgen4 pgen3 pgen2 pgen1 pgen0 mb90460 series 48 8. multi-pulse generator the multi-pulse generator consists of a 16-bit ppg timer, a 16-bit reload timer and a waveform sequencer. by using the waveform sequencer, 16-bit ppg timer output signal can be directed to multi-pulse generator output (opt5 to 0) according to the input signal of multi-pulse generator (sni2 to 0) . meanwhile, the opt5 to 0 output signal can be hardware terminated by dtti input (dtti1) in case of emergency. the opt5 to 0 output signals are synchronized with the ppg signal in order to eliminate the unwanted glitch. the multi-pulse generator has the following features : ? output signal control - 12 output data buffer registers are provided - output data register can be updated by any one of output data buffer registers when : 1. an effective edge detected at sni2 - sni0 pin 2. 16-bit reload timer underflow 3. output data buffer register opdbr0 is written ? output data register (opdr) determines which opt terminals (opt5 - 0) output the 16-bit ppg waveform - waveform sequencer is provided with a 16-bit timer to measure the speed of motor - the 16-bit timer can be used to disable the opt output when the position detection is missing ? input position detect control - sni2 - sni0 input can be used to detect the rotor position - a controllable noise filter is provided to the sni2 - sni0 input ? ppg synchronization for output signal - opt output is able to synchronize the edge of ppg waveform to avoid a short pulse (or glitch) appearance ? vaious interrupt generation causes ?ei 2 os supported mb90460 series 49 block diagram ? block diagram of multi-pulse generator (continued) f 2 mc-16lx bus 16-bit ppg timer 1 16-bit reload timer 0 tout tin ppg1 dtti sni2 sni1 sni0 tin0 pin pin pin pin pin p12/int2/dtti1 p15/int5/tin0 p45/sni2 p44/sni1 p43/sni0 ppg1 win0 tin0o waveform sequencer opt5 opt4 opt3 opt2 opt1 opt0 pin pin pin pin pin pin pin p05/opt5 p04/opt4 p03/opt3 p02/opt2 p01/opt1 p00/opt0 p16/int6/to0 interrupt #22 interrupt #26 interrupt #28 interrupt #22 interrupt #26 interrupt #28 mb90460 series 50 (continued) ? block diagram of waveform sequencer interrupt #22 write timing interrupt opcr register position detection interrupt interrupt #26 pdirt from ppg1 wts1 wts0 syn circuit pin pin pin pin pin pin p00/opt0 p01/opt1 p02/opt2 p03/opt3 p04/opt4 p05/opt5 p12/int2/dtti1 pin d1 d0 noise filter dtti1 control circuit output control circuit dtie dtif nrsl ops2 ops1 ops0 wtif wtie pdif pdie ope5 ope4 ope3 ope2 ope1 ope0 opdbrb to 0 registers output data buffer register 12 decoder opdr register op 1/op 0 rda2 to 0 bnkf 33 compare clear interrupt f 2 mc-16lx bus 16-bit timer wto wtin1 ccirt pin p15/int5/tin0 p43/sni0 p44/sni1 p45/sni2 pin pin pin position detect circuit wtin1 wtin1 3 ops2 ops1 ops0 tin0o data write control unit selector tin0o wtin0 wtin0 wto comparison circuit ipcr register nccr register wts1 wts0 cpif cpie cpd2 cpd1 cpd0 cmpe cpe1 cpe0 snc2 snc1 snc0 see2 see1 see0 pdirt interrupt #28 compare match interrupt d0 d1 s00 s01 s10 s11 s20 s21 mb90460 series 51 9. pwc timer the pwc (pulse width count) timer is a 16-bit multi-function up-counter with reload timer functions and input- signal pulse-width count functions as well. the pwc timer consists of a 16-bit counter, on input pulse divider, a divide ratio control register, a count input pin, a pulse output pin, and a 16-bit control register. the pwc timer has the following features : ? interrupt generated when timer overflow or end of pwc measurement. ?ei 2 os supported ? timer functions : - generates an interrupt request at set time intervals. - outputs pulse signals synchronized with the timer cycle. - selects the counter clock from among three internal clocks. ? pulse-width count functions - counts the time between external pulse input events. - selects the counter clock from among three internal clocks. - count mode h pulse width (rising edge to falling edge) /l pulse width (falling edge to rising edge) rising-edge cycle (rising edge to falling edge) /falling-edge cycle (falling edge to rising edge) count between edges (rising or falling edge to falling or rising edge) capable of counting cycles by dividing input pulses by 2 2 , 2 4 , 2 6 , 2 8 using an 8-bit input divider. generates an interrupt request upon the completion of count operation. selects single or consecutive count operation. mb90460 series 52 block diagram err pwc read pwc reload overflow data transfer 16 16 16 error detection 16 16-bit up count timer control circuit clock f. f. clock divider edge detection f 2 mc-16lx bus write enabled 15 err cks0 cks1 pwcs divr 8-bit divider 2 2 2 2 3 p06/pwi0 p22/pwi1 p07/pwo0 p23/pwo1 division rate selection start edge selection count end edge end edge selection count bit output flag setting divider on/off overflow timer clear count enabled count start edge count end interrupt request overflow interrupt request cks1, cks0, divider clear internal clock (machine clock / 4) mb90460 series 53 10. uart the uart is a serial i/o port for asynchronous (start-stop) communication or clock-synchronous communication. the uart has the following features : ? full-duplex double buffering ? capable of asynchronous (start-stop bit) and clk-synchronous communications ? support for the multiprocessor mode ? various method of baud rate generation : - external clock input possible - internal clock (a clock supplied from 16-bit reload timer can be used.) - embedded dedicated baud rate generator * : assuming internal machine clock frequencies of 6, 8, 10, 12, and 16 mhz ? error detection functions (parity, framing, overrun) ? nrz (non return to zero) signal format ? interrupt request : - receive interrupt (receive complete, receive error detection) - transmit interrupt (transmission complete) - transmit / receive conforms to extended intelligent i/o service (ei 2 os) ? flexible data length : - 7 bit to 9 bit selective (without a parity bit) - 6 bit to 8 bit selective (with a parity bit) operation baud rate asynchronous 31250/9615/4808/2404/1202 bps clk synchronous 2 m/1 m/500 k/250 k/125 k/62.5 kbps mb90460 series 54 block diagram pe ore fre rdrf tdre bds rie tie md1 md0 cs2 cs1 cs0 rst scke soe pen p sbl cl a/d rec rxe txe md div2 div1 div0 sot0, 1 sck0, 1 sin0, 1 clock selector reception control circuit reception clock reception bit counter reception parity counter start bit detection circuit send clock send control circuit send start circuit send bit counter send parity counter reception interrupt request output send interrupt request output end of reception start of transmission reception shift register send shift register reception status determination circuit 16-bit reload timer dedicated baud rate generator control bus pin pin pin serial input data register (0, 1) serial output data register (0, 1) receive error generation signal (to cpu) 2 ei os internal data bus serial status register 0, 1 serial control register 0, 1 serial mode register 0, 1 communication prescaler control register mb90460 series 55 11. dtp/external interrupts the dtp/external interrupt circuit is activated by the signal supplied to a dtp/external interrupt pin. the cpu accepts the signal using the same procedure it uses for normal hardware interrupts and generates external interrupts or activates the extended intelligent i/o service (ei 2 os) . features of dtp/external interrupt : ? total 8 external interrupt channels ? two request levels (h and l) are provided for the intelligent i/o service. ? four request levels (rising edge, falling edge, h level and l level) are provided for external interrupt requests. block diagram lb7 er7 er6 er5 er4 er3 er2 er1 er0 en7 en6 en5 en4 en3 en2 en1 en0 p63/int7 p10/int0/dtti0 la7 lb6 la6 lb5 la5 lb4 la4 lb3 la3 lb2 la2 lb1 la1 lb0 la0 p16/int6/to0 p11/int1 p12/int2/dtti1 p13/int3 p15/int5/tin0 p14/int4 pin pin pin pin pin pin selector selector selector selector pin pin internal data bus selector selector selector selector #20(14 h ) interrupt request number request level setting register (elvr) #22(16 h ) #25(19 h ) #27(1b h ) 2 2 2 2 2 2 2 2 mb90460 series 56 12. delayed interrupt generation module the delayed interrupt generation module is used to generate a task switching interrupt. interrupt requests to the f 2 mc-16lx cpu can be generated and cleared by software using this module. block diagram delayed interrupt cause issuance/cancellation decoder interrupt cause latch f 2 mc- 16lx bus mb90460 series 57 13. a/d converter the converter converts the analog voltage input to an analog input pin (input voltage) to a digital value. the converter has the following features : ? the minimum conversion time is 6.13 m s (for a machine clock of 16 mhz; includes the sampling time) . ? the minimum sampling time is 2.0 m s (for a machine clock of 16 mhz) . ? the converter uses the rc-type successive approximation conversion method with a sample hold circuit. ? a resolution of 10 bits or 8 bits can be selected. ? up to eight channels for analog input pins can be selected by a program. ? various conversion mode : - single conversion mode : selectively convert one channel. - scan conversion mode : continuously convert multiple channels. maximum of 8 program selectable channels. - continuous conversion mode : repeatedly convert specified channels. - stop conversion mode : convert one channel then halt until the next activation. (enables synchronization of the conversion start timing.) ? at the end of a/d conversion, an interrupt request can be generated and ei 2 os can be activated. ? in the interrupt-enabled state, the conversion data protection function prevents any part of the data from being lost through continuous conversion. ? the conversion can be activated by software, 16-bit reload timer 1 (rising edge) and 16-bit free-running timer zero detection edge. mb90460 series 58 block diagram mpx av ss avr d/a converter av cc an0 an1 an2 an3 an4 an5 an6 an7 adcs0/1 adcr0/1 16-bit reload timer 1 16-bit free-running timer zero detection f sequential compare register data register comparator input circuit sample and hold circuit prescaler a/d control register 0 a/d control register 1 operation clock f 2 mc-16lx bus decoder f : machine clock mb90460 series 59 14. rom correction function in the case that the address of the instruction after the one that a program is currently processing matches the address configured in the detection address configuration register, the program forces the next instruction to be processed into an int9 instruction, and branches to the interrupt process program. since processing can be conducted using int9 interrupts, programs can be repaired using batch processing. overview of the rom correction function ? the address of the instruction after the one that a program is currently processing is always stored in an address latch via the internal data bus. address match detection constantly compares the address stored in the address latch with the one configured in the detection address configuration register. if the two compared addresses match, the cpu forcibly changes this instruction into an int9 instruction, and executes an interrupt processing program. ? there are two detection address configuration registers : padr0 and padr1. each register provides an interrupt enable bit. this allows you to individually configure each register to enable/prohibit the generation of interrupts when the address stored in the address latch matches the one configured in the detection address configuration register. block diagram ? address latch stores value of address output to internal data bus. ? address detection control register (pacsr) set this register to enable/prohibit interrupt output when an address match is detected. ? detection address configuration register (padr0, padr1) configure an address with which to compare the address latch value. pacsr padr0 (24 bit) padr1 (24 bit) address latch detection address configuration register 0 detection address configuration register 1 comparator int9 instruction (int9 interrupt generation) re- served re- served re- served ad0e re- served ad1e re- served re- served internal data bus address detection control register (pacsr) reseved : make sure this is always set to 01 mb90460 series 60 15. rom mirroring function selection module the rom mirroring function selection module can select what the ff bank allocated the rom and see through the 00 bank according to register settings. block diagram rom rom mirroring register address area ff bank 00 bank f 2 mc-16lx bus mb90460 series 61 16. 512 kbit flash memory the 512 kbit flash memory is allocated in the fe h to ff h banks on the cpu memory map. like masked rom, flash memory is read-accessible and program-accessible to the cpu using the flash memory interface circuit. the flash memory can be programmed/erased by the instruction from the cpu via the flash memory interface circuit. the flash memory can therefore be reprogrammed (updated) while still on the circuit board under inte- grated cpu control, allowing program code and data to be improved efficiently. note that sector operations such as enable sector protect cannot be used. features of 512 kbit flash memory ? 64 kwords 8 bits/32 kwords 16 bits (16 k + 8 k + 8 k + 32 k) sector configuration ? automatic program algorithm (same as the embedded algorithm* : mbm29f400ta) ? installation of the deletion temporary stop/delete restart function ? write/delete completion detected by the data polling or toggle bit ? write/delete completion detected by the cpu interrupt ? compatibility with the jedec standard-type command ? each sector deletion can be executed (sectors can be freely combined) . ? flash security feature ? number of write/delete operations 10,000 times guaranteed. ? flash reading cycle time (min) 2 machine cycles * : embedded algorithm is a trademark of advanced micro devices, inc. (1) register configuration flash memory control status register bit number address : 0000ae h fmcs read/write initial value r/w 0 r/w 0 r 1 w 0 w 0 w 0 r/w 0 7654 3210 rdyint r/w 0 inte we rdy reserved lpm1 reserved lmp0 mb90460 series 62 (2) sector configuration of 512kbit flash memory the 512 kbit flash memory has the sector configuration illustrated below. the addresses in the illustration are the upper and lower addresses of each sector. when accessed from the cpu, sa0 to sa3 are allocated in the ff bank registers, respectively. * : programmer addresses correspond to cpu addresses when data is programmed in flash memory by a parallel programmer. programmer addresses are used to program/erase data using a general-purpose programmer. ffffff h ffc000 h ffbfff h ffa000 h ff9fff h ff8000 h ff7fff h ff0000 h 7ffff h 7c000 h 7bfff h 7a000 h 79fff h 78000 h 77fff h 70000 h sa3 (16 kbytes) sa2 (8 kbytes) sa1 (8 kbytes) sa0 (32 kbytes) flash memory cpu address *writer address mb90460 series 63 n n n n electrical characteristics 1. absolute maximum ratings (v ss = av ss = 0.0 v) *1 : av cc shall never exceed v cc when power on. *2 : v i and v o shall never exceed v cc + 0.3 v. *3 : the maximum output current is a peak value for a corresponding pin. *4 : applicable to pins : p00 to p07, p10 to p17, p20 to p27, p30 to p37, p40 to p46, p60 to p63 use within recommended operating conditions. use at dc voltage (current) . the + b signal should always be applied with a limiting resistance placed between the + b signal and the microcontroller. the value of the limiting resistance should be set so that when the + b signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. (continued) parameter symbol rating unit remarks min max power supply voltage v cc v ss - 0.3 v ss + 6.0 v av cc v ss - 0.3 v ss + 6.0 v v cc 3 av cc * 1 avr v ss - 0.3 v ss + 6.0 v av cc 3 avr, avr 3 av ss input voltage v i v ss - 0.3 v ss + 6.0 v *2 output voltage v o v ss - 0.3 v ss + 6.0 v *2 maximum clamp current i clamp - 2.0 + 2.0 ma *4 total maximum clamp current s | i clamp | ? 20 ma *4 l level maximum output current i ol ? 15 ma *3 l level average output current i olav ? 4ma average output current = operating current operating efficiency l level total maximum output current s i ol ? 100 ma l level total average output current s i olav ? 50 ma average output current = operating current operating efficiency h level maximum output current i oh ? - 15 ma *3 h level average output current i ohav ? - 4ma average output current = operating current operating efficiency h level total maximum output current s i oh ? - 100 ma h level total average output current s i ohav ? - 50 ma average output current = operating current operating efficiency power consumption p d ? 300 mw operating temperature t a - 40 + 85 c storage temperature tstg - 55 + 150 c mb90460 series 64 (continued) note that when the microcontroller drive current is low, such as in the power saving modes, the + b input potential may pass through the protective diode and increase the potential at the v cc pin, and this may affect other devices. note that if a + b signal is input when the microcontroller current is off (not fixed at 0 v) , the power supply is provided from the pins, so that incomplete operation may result. note that if the + b input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the power-on reset. care must be taken not to leave the + b input pin open. note that analog system input/output pins other than the a/d input pins (lcd drive pins, comparator input pins, etc.) cannot accept + b signal input. sample recommended circuits: warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. p-ch n-ch v cc r ? input/output equivalent circuits + b input (0 v to 16 v) limiting resistance protective diode mb90460 series 65 2. recommended operating conditions (v ss = av ss = 0.0 v) warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter sym- bol value unit remarks min max power supply voltage v cc 3.0 5.5 v normal operation (mb90462, mb90467, mb90v460) 4.5 5.5 v normal operation (mb90f462) v cc 3.0 5.5 v retains status at the time of operation stop smoothing capacitor c s 0.1 1.0 m f use a ceramic capacitor or a capacitor with equiva- lent frequency characteristics. the smoothing capac- itor to be connected to the v cc pin must have a capacitance value higher than c s . operating temperature t a - 40 + 85 c c c s ? c pin connection circuit mb90460 series 66 3. dc characteristics (v cc = 5.0 v 10 % , v ss = av ss = 0.0 v, t a = - 40 c to + 85 c) (continued) parameter sym- bol pin name condition value unit remarks min typ max h level output voltage v oh all output pins v cc = 4.5 v, i oh = - 4.0 ma v cc - 0.5 ?? v l level output voltage v ol all pins except p00 to p05 and p30 to p35 v cc = 4.5 v, i ol = 4.0 ma ?? 0.4 v p00 to p05, p30 to p35 v cc = 4.5 v, i ol = 12.0 ma ?? 0.4 v h level input voltage v ih p00 to p07 p30 to p37 p50 to p57 v cc = 3.0 v to 5.5 v (mb90462) v cc = 4.5 v to 5.5 v (mb90f462) 0.7 v cc ? v cc + 0.3 v cmos input pin v ihs p10 to p17 p20 to p27 p40 to p46 p60 to p63, rst 0.8 v cc ? v cc + 0.3 v cmos hyster- esis input pin v ihm md pins v cc - 0.3 ? v cc + 0.3 v md pin input l level input voltage v il p00 to p07 p30 to p37 p50 to p57 v ss - 0.3 ? 0.3 v cc v cmos input pin v ils p10 to p17 p20 to p27 p40 to p46 p60 to p63, rst v ss - 0.3 ? 0.2 v cc v cmos hyster- esis input pin v ilm md pins v ss - 0.3 ? v ss + 0.3 v md pin input input leakage current i il all input pins v cc = 5.5 v, v ss < v i < v cc - 5 ? 5 m a power supply current* i cc v cc v cc = 5.0 v, internal opera- tion at 16 mhz, normal operation ? 40 50 ma v cc = 5.0 v, internal opera- tion at 16 mhz, when data writ- ten in flash mode programming of erasing ? 45 60 ma i ccs v cc = 5.0 v, internal opera- tion at 16 mhz, in sleep mode ? 15 20 ma mb90460 series 67 (continued) (v cc = 5.0 v 10 % , v ss = av ss = 0.0 v, t a = - 40 c to + 85 c) * : the current value is preliminary value and may be subject to change for enhanced characteristics without previous notice. the power supply current is measured with an external clock. parameter sym- bol pin name condition value unit remarks min typ max power supply current* i cts v cc v cc = 5.0 v, internal opera- tion at 16 mhz, in timer mode, t a = 25 c ? 2.5 5.0 ma i cch in stop mode, t a = 25 c ? 520 m a input capacitance c in except av cc , av ss , c, v cc and v ss ?? 10 80 pf pull-up resistance r up p00 to p07 p10 to p17 rst ? 25 50 100 k w pull-down resistance r down md2 ? 25 50 100 k w mb90460 series 68 4. ac characteristics (1) clock timings (v cc = 5.0 v 10 % , v ss = av ss = 0.0 v, t a = - 40 c to + 85 c) *1 : the frequency fluctuation rate is the maximum deviation rate of the preset center frequency when the multiplied pll signal is locked. *2 : internal operating clock frequency must not be over 16 mhz. parameter symbol pin name value unit remarks min typ max clock frequency f c x0, x1 3 ? 16 mhz crystal oscillator 3 ? 32 external clock * 2 clock cycle time t hcyl x0, x1 62.5 ? 333 ns frequency fluctuation rate locked* 1 d f ??? 5 % input clock pulse width p wh p wl x0 10 ?? ns recommened duty ratio of 30 % to 70 % input clock rise/fall time t cr t cf x0 ?? 5 ns external clock operation internal operating clock f cp ? 1.5 ? 16 mhz main clock operation internal operating clock cycle time t cp ? 62.5 ? 666 ns main clock operation +a a fo fo -a d f = 100 (%) center frequency 0.8 v cc 0.2 v cc t cf t cr t hcyl p wh p wl x0 mb90460 series 69 the ac ratings are measured for the following measurement reference voltages relationship between internal operating clock frequency and power supply voltage relationship between oscillating frequency and internal operating clock frequency 5.5 4.5 3.0 3.3 8 internal clock f cp (mhz) power supply voltage v cc (v) 1 3 12 16 operation guarantee range of mb90f462 operation guarantee range of pll operation guarantee range of mb90462, mb90467, mb90v460 16 12 8 9 4 34 8 oscillation clock f c (mhz) internal clock f cp (mhz) 16 multiplied- by-4 multiplied- by-3 multiplied- by-2 multiplied- by-1 not multiplied 0.8 v cc 0.2 v cc 2.4 v 0.8 v 0.7 v cc 0.3 v cc ? input signal waveform hysteresis input pin pin other than hystheresis input/md input ? output signal waveform output pin mb90460 series 70 (2) reset input timing (v cc = 5.0 v 10 % , v ss = av ss = 0.0 v, t a = - 40 c to + 85 c) * : oscillation time of oscillator is time that amplitude reached the 90 % . in the crystal oscillator, the oscillation time is between several ms to tens of ms. in far/ceramic oscillator, the oscillation time is between handreds m s to several ms. in the external clock, the oscillation time is 0 ms. parameter symbol pin condition value units remarks min max reset input time t rstl rst ? 4 t cp ? ns under normal operation oscillation time of oscillator + 4 t cp * ? ms in stop mode t rstl 0.2 v cc 0.2 v cc 4 t cp rst x0 internal operation clock internal reset 90% of amplitude oscillation time of oscillator oscillation setting time instruction execution ? in stop mode mb90460 series 71 (3) power-on reset (v cc = 5.0 v 10 % , v ss = av ss = 0.0 v, t a = - 40 c to + 85 c) note : v cc must be kept lower than 0.2 v before power-on. the above values are used for causing a power-on reset. some registers in the device are initialized only upon a power-on reset. to initialize these registers, turn the power supply using the above values. parameter symbol pin name condition value unit remarks min max power supply rising time t r v cc ? 0.05 30 ms power supply cut-off time t off v cc 4 ? ms due to repeated operations v cc v cc v ss 3.0 v t r t off 2.7 v 0.2 v 0.2 v 0.2 v ram data hold sudden changes in the power supply voltage may cause a power-on reset. to change the power supply voltage while the device is in operation, it is recommended to raise the voltage smoothly to suppress fluctuations as shown below. in this case, change the supply voltage with the pll clock not used. if the voltage drop is 1 v or fewer per second, however, you can use the pll clock. it is recommended to keep the rising speed of the supply voltage at 50 mv/ms or slower. mb90460 series 72 (4) uart0 to uart1 (v cc = 5.0 v 10 % , v ss = av ss = 0.0 v, t a = - 40 c to + 85 c) note : these are ac ratings in the clk synchronous mode. cl is the load capacitance value connected to pins while testing. t cp is machine cycle time (unit : ns) . parameter symbol pin name condition value unit remarks min max serial clock cycle time t scyc sck0 to sck1 c l = 80 pf + 1 ttl for an output pin of internal shift clock mode 8 t cp ? ns sck ? sot delay time t slov sck0 to sck1 sot0 to sot1 - 80 80 ns valid sin ? sck - t ivsh sck0 to sck1 sin0 to sin1 100 ? ns sck - ? valid sin hold time t shix sck0 to sck1, sin0 to sin1 60 ? ns serial clock h pulse width t shsl sck0 to sck1 c l = 80 pf + 1 ttl for an output pin of external shift clock mode 4 t cp ? ns serial clock l pulse width t slsh sck0 to sck1 4 t cp ? ns sck ? sot delay time t slov sck0 to sck1, sot0 to sot1 ? 150 ns valid sin ? sck - t ivsh sck0 to sck1, sin0 to sin1 60 ? ns sck - ? valid sin hold time t shix sck0 to sck1, sin0 to sin1 60 ? ns mb90460 series 73 ? internal shift clock mode ? external shift clock mode sck sot sin t scyc t slov t ivsh t shix 0.8 v 0.8 v 2.4 v 2.4 v 0.8 v 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc sck sot sin t slsh t shsl t slov t ivsh t shix 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc 2.4 v 0.8 v 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc mb90460 series 74 (5) resources input timing (v cc = 5.0 v 10 % , v ss = av ss = 0.0 v, t a = - 40 c to + 85 c) (6) trigger input timimg (v cc = 5.0 v 10 % , v ss = av ss = 0.0 v, t a = - 40 c to + 85 c) parameter symbol pin name condition value unit remarks min max input pulse width t tiwh t tiwl in0 to in3, sni0 to sni2 tin0 to tin1 pwi0 to pwi1 dtti0, dtti1 ? 4 t cp ? ns parameter symbol pin name condition value unit remarks min max input pulse width t trgh t trgl int0 to int7 ? 5 t cp ? ns 0.8 v cc *1 0.8 v cc 0.2 v cc *2 0.2 v cc *2 t tiwh t tiwl *1 : 0.7 v cc for pwi0 input pin *2 : 0.3 v cc for pwi0 input pin 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc t trgh t trgl mb90460 series 75 5. a/d converter electrical characteristics (3.0 v avr - av ss , v cc = av cc = 5.0 v 10 % , v ss = av ss = 0.0 v, t a = - 40 c to + 85 c) * : the current when the a/d converter is not operating or the cpu is in stop mode (for v cc = av cc = avr = 5.0 v) parameter sym- bol pin name value unit remarks min typ max resolution ?? ? 10 ? bit total error ?? ? ? 3.0 lsb for mb90f462, mb90462, mb90467 ?? ? ? 5.0 lsb for mb90v460 non-linear error ?? ? ? 2.5 lsb differential linearity error ?? ? ? 1.9 lsb zero transition voltage v ot an0 to an7 av ss - 1.5 lsb av ss + 0.5 lsb av ss + 2.5 lsb mv for mb90f462, mb90462, mb90467 av ss - 3.5 lsb av ss + 0.5 lsb av ss + 4.5 lsb mv for mb90v460 full-scale transition voltage v fst an0 to an7 avr - 3.5 lsb avr - 1.5 lsb avr + 0.5 lsb mv for mb90f462, mb90462, mb90467 avr - 6.5 lsb avr - 1.5 lsb avr + 1.5 lsb mv for mb90v460 conversion time ?? 6.125 ? 1000 m s actual value is specified as a sum of values specified in adcr0 : ct1, ct0 and adcr0 : st1, st0. be sure that the setting value is greater than the min value sampling period ?? 2 ??m s actual value is specified in adcr0 : st1, st0 bits. be sure that the set- ting value is greater than the min val- ue analog port input current i ain an0 to an7 ?? 10 m a analog input voltage v ain an0 to an7 av ss ? avr v reference voltage ? avr av ss + 2.7 ? av cc v power supply current i a av cc ? 2.3 6 ma for mb90f462, mb90462, mb90467 ? 2 5 ma for mb90v460 i ah * ?? 5 m a* reference voltage supply current ir avr ? 140 260 m a for mb90f462, mb90462, mb90467 ? 0.9 1.3 ma for mb90v460 i rh * ?? 5 m a* offset between channels ? an0 to an7 ?? 4lsb mb90460 series 76 6. a/d converter glossary (continued) resolution : analog changes that are identifiable with the a/d converter linearity error : the deviation of the straight line connecting the zero transition point (00 0000 0000 ?? 000000 0001) with the full-scale transition point (11 1111 1110 ?? 11 1111 1111) from actual conversion characteristics differential linearity error : the deviation of input voltage needed to change the output code by 1 lsb from the theoretical value total error : the total error is defined as a difference between the actual value and the theoretical value, which includes zero-transition error/full-scale transition error and linearity error. 3ff 3fe 3fd 004 003 002 001 avss digital output avr analog input 1.5 lsb 0.5 lsb {1 lsb (n - 1) + 0.5 lsb} actual conversion value actual conversion value theoretical characteristics v nt (measured value) total error total error for digital output n = v nt - {1 lsb (n - 1) + 0.5 lsb} [lsb] 1 lsb 1 lsb = (theoretical value) avr - av ss [v] 1024 v ot (theoretical value) = av ss + 0.5 lsb [v] v fst (theoretical value) = avr - 1.5 lsb [v] v nt : voltage at a transition of digital output from (n - 1) to n mb90460 series 77 (continued) 3ff 3fe 3fd 004 003 002 001 avss avr avss avr n + 1 n n - 1 n - 2 v nt v ( n + 1) t v ot (measured value) v fst {1 lsb (n - 1) + v ot } digital output digital output analog input analog input actual conversion value (measured value) actual conversion value theoretical characteristics (measured value) theoretical characteristics actual conversion value (measured value) actual conversion value v nt (measured value) differential linearity error linearity error linearity error of digital output n v nt - {1 lsb (n - 1) + v ot } = 1 lsb [lsb] differential linearity error of digital output n v ( n + 1 ) t - v nt = 1 lsb - 1 [lsb] v fst - v ot = 1022 [v] 1 lsb v ot : voltage at transition of digital output from 000 h to 001 h v fst : voltage at transition of digital output from 3fe h to 3ff h mb90460 series 78 7. notes on using a/d converter select the output impedance value for the external circuit of analog input according to the following conditions. output impedance values of the external circuit recommends about 5 k w or lower (sampling period = 2.0 m s @machine clock of 16 mhz) . when capacitors are connected to external pins, the capacitance of several thousand times the internal capacitor value is recommended to minimized the effect of voltage distribution between the external capacitor and internal capacitor. when the output impedance of the external circuit is too high, the sampling period for analog voltages may not be sufficient. ? error the smaller the absolute value of | avr - av ss |, the greater the error would become relatively. 8. flash memory program and erase performances parameter condition value unit remarks min typ max sector erase time t a = + 25 c v cc = 3.0 v ? 115s excludes 00h programming prior erasure chip erase time ? 5 ? s excludes 00 h program- ming prior erasure word (16 bit width) programming time ? 16 3,600 m s excludes system-level overhead erase/program cycle ? 10,000 ?? cycle c comparator analog input r ? analog input circuit model note : listed values must be considered as standards. mb90462, mb90f462, mb90467 r @ 2.6 k w , c @ 28 pf mb90v460 r @ 3.2 k w , c @ 30 pf mb90460 series 79 n n n n example characteristics ? power suppy current of mb90462, mb90467 40 35 30 25 20 15 10 5 0 234 56 i cch (ma) f c = 16 [mhz] f c = 12 [mhz] f c = 10 [mhz] f c = 8 [mhz] f c = 4 [mhz] f c = 2 [mhz] v cc (v) i ccs (ma) 23456 f c = 4 [mhz] f c = 12 [mhz] f c = 16 [mhz] f c = 10 [mhz] f c = 8 [mhz] f c = 2 [mhz] 20 18 16 14 12 10 8 6 4 2 0 v cc (v) v cc - v oh (mv) i oh (ma) 1000 900 800 700 600 500 400 300 200 100 0 024681012 - - -- -- v ol (v) i ol (ma) 1000 900 800 700 600 500 400 300 200 100 0 024681012 i cch vs. v cc t a = 25 c, external clock input i ccs vs. v cc t a = 25 c, external clock input v cc - v oh vs. i oh t a = 25 c, v cc = 4.5 v v ol vs. i ol t a = 25 c, v cc = 4.5 v mb90460 series 80 ? power suppy current of mb90f462 40 35 30 25 20 15 10 5 0 234 56 i cch (ma) f c = 16 [mhz] f c = 12 [mhz] f c = 10 [mhz] f c = 8 [mhz] f c = 4 [mhz] f c = 2 [mhz] v cc (v) i ccs (ma) 23456 f c = 4 [mhz] f c = 12 [mhz] f c = 10 [mhz] f c = 8 [mhz] f c = 2 [mhz] 20 18 16 14 12 10 8 6 4 2 0 f c = 16 [mhz] v cc (v) v cc - v oh (mv) i oh (ma) 1000 900 800 700 600 500 400 300 200 100 0 024681012 v ol (v) i ol (ma) 1000 900 800 700 600 500 400 300 200 100 0 024681012 i cch vs. v cc t a = 25 c, external clock input i ccs vs. v cc t a = 25 c, external clock input v cc - v oh vs. i oh t a = 25 c, v cc = 4.5 v v ol vs. i ol t a = 25 c, v cc = 4.5 v mb90460 series 81 n n n n ordering information part number package remarks mb90f462pfm mb90462pfm mb90467pfm 64-pin plastic lqfp (fpt-64p-m09) mb90f462pf mb90462pf mb90467pf 64-pin plastic qfp (fpt-64p-m06) mb90f462p-sh MB90462P-SH mb90467p-sh 64-pin plastic sh-dip (dip-64p-m01) mb90460 series 82 n n n n package dimensions 64-pin plastic qfp (fpt-64p-m06) note : pins width and pins thickness include plating thickness. dimensions in mm (inches) c 2001 fujitsu limited f64013s-c-4-4 0.20(.008) m 18.70?.40 (.736?016) 14.00?.20 (.551?008) 1.00(.039) index 0.10(.004) 119 20 32 52 64 33 51 20.00?.20(.787?008) 24.70?.40(.972?016) 0.42?.08 (.017?003) 0.17?.06 (.007?002) 0~8 1.20?.20 (.047?008) 3.00 +0.35 ?.20 (mounting height) .118 +.014 ?008 0.25 +0.15 ?.20 .010 +.006 ?008 (stand off) details of "a" part "a" 0.10(.004) mb90460 series 83 64-pin plastic lqfp (fpt-64p-m09) note : pins width and pins thickness include plating thickness. dimensions in mm (inches) c 2001 fujitsu limited f64018s-c-2-4 0.65(.026) 0.10(.004) 116 17 32 49 64 33 48 12.00?.10(.472?004)sq 14.00?.20(.551?008)sq index 0.32?.05 (.013?002) m 0.13(.005) 0.145?.055 (.0057?0022) "a" .059 ?004 +.008 ?.10 +0.20 1.50 0~8 0.25(.010) (mounting height) 0.50?.20 (.020?008) 0.60?.15 (.024?006) 0.10?.10 (.004?004) details of "a" part (stand off) 0.10(.004) mb90460 series 84 64-pin plastic sh-dip (dip-64p-m01) note : pins width and pins thickness include plating thickness. dimensions in mm (inches) c 2001 fujitsu limited d64001s-c-4-5 58.00 +0.22 ?.55 +.009 ?022 2.283 17.00?.25 (.669?010) 3.30 +0.20 ?.30 .130 ?012 +.008 +.028 ?008 .195 ?.20 +0.70 4.95 +.016 ?008 .0543 ?.20 +0.40 1.378 1.778(.0700) 0.47?.10 (.019?004) 1.00 +0.50 ? .039 ?0 +.020 +.020 ?007 .028 ?.19 +0.50 0.70 19.05(.750) (.011?004) 0.27?.10 0~15 index-2 index-1 m 0.25(.010) mb90460 series fujitsu limited for further information please contact: japan fujitsu limited marketing division electronic devices shinjuku dai-ichi seimei bldg. 7-1, nishishinjuku 2-chome, shinjuku-ku, tokyo 163-0721, japan tel: +81-3-5322-3353 fax: +81-3-5322-3386 http://edevice.fujitsu.com/ north and south america fujitsu microelectronics america, inc. 3545 north first street, san jose, ca 95134-1804, u.s.a. tel: +1-408-922-9000 fax: +1-408-922-9179 customer response center mon. - fri.: 7 am - 5 pm (pst) tel: +1-800-866-8608 fax: +1-408-922-9179 http://www.fma.fujitsu.com/ europe fujitsu microelectronics europe gmbh am siebenstein 6-10, d-63303 dreieich-buchschlag, germany tel: +49-6103-690-0 fax: +49-6103-690-122 http://www.fme.fujitsu.com/ asia pacific fujitsu microelectronics asia pte. ltd. #05-08, 151 lorong chuan, new tech park, singapore 556741 tel: +65-281-0770 fax: +65-281-0220 http://www.fmal.fujitsu.com/ korea fujitsu microelectronics korea ltd. 1702 kosmo tower, 1002 daechi-dong, kangnam-gu,seoul 135-280 korea tel: +82-2-3484-7100 fax: +82-2-3484-7111 f0112 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). please note that fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan. |
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